L1 and Ln cache: when are they written?Why can L3 caches hold only shared blocks?Multi-level cache for which inclusion holdsMESI Protocol Invalid cache line is attempted to be stored?Back invalidation to maintain inclusion in inclusive cacheComputer Architecture, cache hit and missesWhat if block sizes are not equal among caches?Pros and Cons of Average Memory Access Time When Increasing Cache Block SizeDirect-mapping cache questionCalculate Miss rate of L2 cache given global and L1 miss ratesSet Associative Cache Exercises
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L1 and Ln cache: when are they written?
Why can L3 caches hold only shared blocks?Multi-level cache for which inclusion holdsMESI Protocol Invalid cache line is attempted to be stored?Back invalidation to maintain inclusion in inclusive cacheComputer Architecture, cache hit and missesWhat if block sizes are not equal among caches?Pros and Cons of Average Memory Access Time When Increasing Cache Block SizeDirect-mapping cache questionCalculate Miss rate of L2 cache given global and L1 miss ratesSet Associative Cache Exercises
$begingroup$
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
If I have a multilevel cache, L1/L2/L3/Ln:
1) what decides what level of this hierarchy a block fetched from memory initially gets put in?
2) If I evict a block from L1, does that mean it gets moved to L2 (replacing a block from L2 depending on the replacement policy), and so forth for L2 to L3, and L3 to Ln, until the block evicted from the last level cache gets written to memory?
PS And yes, I have searched for this, so don't downvote assuming I haven't :)
Update
After the answer given below, I went back to the video course and found this. It seems to suggest that data is initially fetched into the L2 cache, then "fed" to the L1 cache. This also shows how, without the inclusion bit set, L1 and L2 can become "out of sync".
3) Is this generally what happens in all caches? IE if I have a 7 layer cache, will the block be fetched into L7, then fed L7->L6, L6->L5 ... and finally L2->L1? This seems like a lot of work...
4) Except in the situation shown in the linked video (if the caches get "out of sync" then certain data will only be available in one cache even though it started out in both caches), it seems that having the same data in multiple levels of the cache all the time (i.e. when the inclusion bit is set) is a waste; we have to copy it amongst all the levels. This can't be the case though, so what am I missing?
cpu-cache
asked 4 hours ago
WadWad
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
If I have a multilevel cache, L1/L2/L3/Ln:
1) what decides what level of this hierarchy a block fetched from memory initially gets put in?
2) If I evict a block from L1, does that mean it gets moved to L2 (replacing a block from L2 depending on the replacement policy), and so forth for L2 to L3, and L3 to Ln, until the block evicted from the last level cache gets written to memory?
PS And yes, I have searched for this, so don't downvote assuming I haven't :)
Update
After the answer given below, I went back to the video course and found this. It seems to suggest that data is initially fetched into the L2 cache, then "fed" to the L1 cache. This also shows how, without the inclusion bit set, L1 and L2 can become "out of sync".
3) Is this generally what happens in all caches? IE if I have a 7 layer cache, will the block be fetched into L7, then fed L7->L6, L6->L5 ... and finally L2->L1? This seems like a lot of work...
4) Except in the situation shown in the linked video (if the caches get "out of sync" then certain data will only be available in one cache even though it started out in both caches), it seems that having the same data in multiple levels of the cache all the time (i.e. when the inclusion bit is set) is a waste; we have to copy it amongst all the levels. This can't be the case though, so what am I missing?
cpu-cache
asked 4 hours ago
WadWad
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
If I have a multilevel cache, L1/L2/L3/Ln:
1) what decides what level of this hierarchy a block fetched from memory initially gets put in?
2) If I evict a block from L1, does that mean it gets moved to L2 (replacing a block from L2 depending on the replacement policy), and so forth for L2 to L3, and L3 to Ln, until the block evicted from the last level cache gets written to memory?
PS And yes, I have searched for this, so don't downvote assuming I haven't :)
Update
After the answer given below, I went back to the video course and found this. It seems to suggest that data is initially fetched into the L2 cache, then "fed" to the L1 cache. This also shows how, without the inclusion bit set, L1 and L2 can become "out of sync".
3) Is this generally what happens in all caches? IE if I have a 7 layer cache, will the block be fetched into L7, then fed L7->L6, L6->L5 ... and finally L2->L1? This seems like a lot of work...
4) Except in the situation shown in the linked video (if the caches get "out of sync" then certain data will only be available in one cache even though it started out in both caches), it seems that having the same data in multiple levels of the cache all the time (i.e. when the inclusion bit is set) is a waste; we have to copy it amongst all the levels. This can't be the case though, so what am I missing?
cpu-cache
asked 4 hours ago
WadWad
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
If I have a multilevel cache, L1/L2/L3/Ln:
1) what decides what level of this hierarchy a block fetched from memory initially gets put in?
2) If I evict a block from L1, does that mean it gets moved to L2 (replacing a block from L2 depending on the replacement policy), and so forth for L2 to L3, and L3 to Ln, until the block evicted from the last level cache gets written to memory?
PS And yes, I have searched for this, so don't downvote assuming I haven't :)
Update
After the answer given below, I went back to the video course and found this. It seems to suggest that data is initially fetched into the L2 cache, then "fed" to the L1 cache. This also shows how, without the inclusion bit set, L1 and L2 can become "out of sync".
3) Is this generally what happens in all caches? IE if I have a 7 layer cache, will the block be fetched into L7, then fed L7->L6, L6->L5 ... and finally L2->L1? This seems like a lot of work...
4) Except in the situation shown in the linked video (if the caches get "out of sync" then certain data will only be available in one cache even though it started out in both caches), it seems that having the same data in multiple levels of the cache all the time (i.e. when the inclusion bit is set) is a waste; we have to copy it amongst all the levels. This can't be the case though, so what am I missing?
cpu-cache
cpu-cache
asked 4 hours ago
WadWad
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 4 hours ago
WadWad
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
edited 1 hour ago
Wad
asked 4 hours ago
WadWad
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 4 hours ago
WadWad
1063
asked 4 hours ago
WadWad
1063
1063
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Wad is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
add a comment |
1 Answer
1
active
oldest
votes
$begingroup$
1) Usually any accessed data are saved into L1, independent whether they were previously available in L1, L2... or memory only.
For exclusive cache, data are stored ONLY in L1, for inclusive one, in the entire hierarchy. There are also mixed strategies. Also, some CPUs have "victim cache", which is extra cache level which gets ONLY data moved out of LLC (last level cache).
2) Yes, for write-back exclusive cache.
3) You misunderstood his explanation. He said that data are fetched and placed to both caches. Inclusion, btw, isn't the "bit set", but entire cache policy. The policy is built right into the hardware.
4) Exclusive cache better use precious space, but each time you have to bring new block into L1, you have to displace some block to L2, then some one to L3... and finally some one to memory. This means a lot of work. With inclusive cache, you just drop data from L1 cache, or replace older copy in L2 with newer copy displaced from L1.
As result, exclusive strategy is more optimal when adjacent cache levels has closer sizes (f.e. <=4x) and inclusive is better when sizes are very different.
answered 4 hours ago
BulatBulat
796410
$endgroup$
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
|
show 1 more comment
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1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
1) Usually any accessed data are saved into L1, independent whether they were previously available in L1, L2... or memory only.
For exclusive cache, data are stored ONLY in L1, for inclusive one, in the entire hierarchy. There are also mixed strategies. Also, some CPUs have "victim cache", which is extra cache level which gets ONLY data moved out of LLC (last level cache).
2) Yes, for write-back exclusive cache.
3) You misunderstood his explanation. He said that data are fetched and placed to both caches. Inclusion, btw, isn't the "bit set", but entire cache policy. The policy is built right into the hardware.
4) Exclusive cache better use precious space, but each time you have to bring new block into L1, you have to displace some block to L2, then some one to L3... and finally some one to memory. This means a lot of work. With inclusive cache, you just drop data from L1 cache, or replace older copy in L2 with newer copy displaced from L1.
As result, exclusive strategy is more optimal when adjacent cache levels has closer sizes (f.e. <=4x) and inclusive is better when sizes are very different.
answered 4 hours ago
BulatBulat
796410
$endgroup$
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
|
show 1 more comment
$begingroup$
1) Usually any accessed data are saved into L1, independent whether they were previously available in L1, L2... or memory only.
For exclusive cache, data are stored ONLY in L1, for inclusive one, in the entire hierarchy. There are also mixed strategies. Also, some CPUs have "victim cache", which is extra cache level which gets ONLY data moved out of LLC (last level cache).
2) Yes, for write-back exclusive cache.
3) You misunderstood his explanation. He said that data are fetched and placed to both caches. Inclusion, btw, isn't the "bit set", but entire cache policy. The policy is built right into the hardware.
4) Exclusive cache better use precious space, but each time you have to bring new block into L1, you have to displace some block to L2, then some one to L3... and finally some one to memory. This means a lot of work. With inclusive cache, you just drop data from L1 cache, or replace older copy in L2 with newer copy displaced from L1.
As result, exclusive strategy is more optimal when adjacent cache levels has closer sizes (f.e. <=4x) and inclusive is better when sizes are very different.
answered 4 hours ago
BulatBulat
796410
$endgroup$
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
|
show 1 more comment
$begingroup$
1) Usually any accessed data are saved into L1, independent whether they were previously available in L1, L2... or memory only.
For exclusive cache, data are stored ONLY in L1, for inclusive one, in the entire hierarchy. There are also mixed strategies. Also, some CPUs have "victim cache", which is extra cache level which gets ONLY data moved out of LLC (last level cache).
2) Yes, for write-back exclusive cache.
3) You misunderstood his explanation. He said that data are fetched and placed to both caches. Inclusion, btw, isn't the "bit set", but entire cache policy. The policy is built right into the hardware.
4) Exclusive cache better use precious space, but each time you have to bring new block into L1, you have to displace some block to L2, then some one to L3... and finally some one to memory. This means a lot of work. With inclusive cache, you just drop data from L1 cache, or replace older copy in L2 with newer copy displaced from L1.
As result, exclusive strategy is more optimal when adjacent cache levels has closer sizes (f.e. <=4x) and inclusive is better when sizes are very different.
answered 4 hours ago
BulatBulat
796410
$endgroup$
1) Usually any accessed data are saved into L1, independent whether they were previously available in L1, L2... or memory only.
For exclusive cache, data are stored ONLY in L1, for inclusive one, in the entire hierarchy. There are also mixed strategies. Also, some CPUs have "victim cache", which is extra cache level which gets ONLY data moved out of LLC (last level cache).
2) Yes, for write-back exclusive cache.
3) You misunderstood his explanation. He said that data are fetched and placed to both caches. Inclusion, btw, isn't the "bit set", but entire cache policy. The policy is built right into the hardware.
4) Exclusive cache better use precious space, but each time you have to bring new block into L1, you have to displace some block to L2, then some one to L3... and finally some one to memory. This means a lot of work. With inclusive cache, you just drop data from L1 cache, or replace older copy in L2 with newer copy displaced from L1.
As result, exclusive strategy is more optimal when adjacent cache levels has closer sizes (f.e. <=4x) and inclusive is better when sizes are very different.
answered 4 hours ago
BulatBulat
796410
edited 46 mins ago
answered 4 hours ago
BulatBulat
796410
answered 4 hours ago
BulatBulat
796410
answered 4 hours ago
BulatBulat
796410
796410
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
|
show 1 more comment
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
Thanks for responding. I have updated the original question after reviewing your comment and using it to search the course I linked to: could you please check my update and update your answer? Thanks!
$endgroup$
– Wad
1 hour ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
@Wad done......
$endgroup$
– Bulat
59 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
Thank you for taking the time to edit your answer. I don't understand 3) and 4) however, sorry. 3) So in an N level cache, what level is written to first when we have a miss? Is it N? And if so, is that same block copied to all higher levels? 4) Regarding exclusive, why do you need to displace from L1 to L2? Is this what I questioned in 2) above that you answered? Inclusion: surely this involves the most work, copying a block across all N caches??
$endgroup$
– Wad
40 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
@Wad 3) Data are written into all cache levels simultaneously. It can be done since all hardware in the CPU can work simultaneously. Physically, it can be done earlier or later. What is really important for us is that data become available for following operations so next access to A will be done at L1 speed. (Of course, in exclusive cache data are written only into L1)
$endgroup$
– Bulat
21 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
$begingroup$
4) In exclusive cache, when you displace data from L1, they absent in L2. So you should save them there for the case they will be used again (and it's the only way anything can be written to L2 when caches are exclusive)
$endgroup$
– Bulat
14 mins ago
|
show 1 more comment
Wad is a new contributor. Be nice, and check out our Code of Conduct.
Wad is a new contributor. Be nice, and check out our Code of Conduct.
Wad is a new contributor. Be nice, and check out our Code of Conduct.
Wad is a new contributor. Be nice, and check out our Code of Conduct.
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